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INTEGRATED CIRCUITS
74ALS563A/74ALS564A Latch flip/flop
Product specification IC05 Data Handbook 1996 Jul 01
Philips Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A 74ALS564A
FEATURES
74ALS373
74ALS563A/74ALS564A
Octal transparent latch, inverting (3-State) Octal D flip-flop, inverting (3-State)
DESCRIPTION
The 74ALS563A is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 74ALS563A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the inverted data that is present one setup time before the High-to-Low enable transition. The 74ALS564A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. DRAWING NUMBER
* 74ALS563A is broadside pinout and inverting version of * 74ALS564A is broadside pinout and inverting version of
74ALS374
* Inputs and outputs on opposite side of package allow easy
interface to microprocessors
* Useful as an input or output port for microprocessors * 3-State outputs for bus interfacing * Common output enable * 74ALS573A and 74ALS574A are non-inverting version of
74ALS563B and 74ALS564A respectively TYPICAL SUPPLY CURRENT (TOTAL) 12mA 15mA
TYPE 74ALS563A 74ALS564A
TYPICAL PROPAGATION DELAY 6.0ns 6.0ns
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 74ALS563AN, 74ALS564AN 74ALS563AD, 74ALS564AD
20-pin plastic DIP 20-pin plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 E (74ALS563A) OE CP (74ALS564A) Q0 - Q7 Data inputs Enable input Output enable input (active-Low) Clock pulse input (active rising edge) Data outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 130/240 LOAD VALUE HIGH/LOW 20A/0.2mA 20A/0.1mA 20A/0.1mA 20A/0.2mA 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20A in the High state and 0.1mA in the Low state.
1996 Jul 01
2
853-1306 01670
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
PIN CONFIGURATION - 74ALS563A
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E
PIN CONFIGURATION - 74ALS564A
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
GND 10
GND 10
SC00111
SF01052
LOGIC SYMBOL - 74ALS563A
LOGIC SYMBOL - 74ALS564A
2 3 4 5 6 7 8 9
2
3
4
5
6
7
8
9 D0 D1 D2 D3 D4 D5 D6 D7
D0 11 E
D1
D2
D3
D4
D5
D6
D7
11
CP
1 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 19 VCC=Pin 20 GND=Pin 10 18 17 16 15 14 13 12 VCC=Pin 20 GND=Pin 10
18
17
16
15
14
13
12
SC00112
SF01053
IEC/IEEE SYMBOL - 74ALS563A
1 11 EN2 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 EN1
IEC/IEEE SYMBOL - 74ALS564A
1 11 C2 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 EN1
2D
1
2D
1
SC00113
SF01054
1996 Jul 01
3
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
LOGIC DIAGRAM - 74ALS563A
D0 2 D E E 11 D1 3 D E D2 4 D E D3 5 D E D4 6 D E D5 7 D E D6 8 D E D7 9 D E
Q
Q
Q
Q
Q
Q
Q
Q
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC = Pin 20 GND = Pin 10
Q0
SC00116
FUNCTION TABLE - 74ALS563A
INPUTS OE L L L L L H H H= h= L= l= NC= X= Z= = E H H L L H Dn L H l h X X Dn OUTPUTS REGISTER L H L H NC NC Dn INTERNAL Q0 - Q7 H L H L NC Z Z Disable outputs Latch and read register Hold Enable and read register OPERATING MODE
High voltage level High state must be present one setup time before the High-to-Low enable transition Low voltage level Low state must be present one setup time before the High-to-Low enable transition No change Don't care High impedance "off" state High-to-Low enable transition
1996 Jul 01
4
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
LOGIC DIAGRAM - 74ALS564A
D0 2 D CP Q CP 11 D1 3 D CP Q D2 4 D CP Q D3 5 D CP Q D4 6 D CP Q D5 7 D CP Q D6 8 D CP Q D7 9 D CP Q
OE VCC = Pin 20 GND = Pin 10
1 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
SC00117
FUNCTION TABLE - 74ALS564A
INPUTS OE L L L H H H= h= L= l= NC= X= Z= = = CP Dn l h X X Dn OUTPUTS REGISTER L H NC NC Dn INTERNAL Q0 - Q7 H L NC Z Z Disable outputs Load and read register Hold OPERATING MODE
High voltage level High state must be present one setup time before the Low-to-High clock transition Low voltage level Low state must be present one setup time before the Low-to-High clock transition No change Don't care High impedance "off " state Low-to-High clock transition Not Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
1996 Jul 01
5
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -2.6 24 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 MIN VO OH High-level High level output voltage VCC = 10%, VIL = MAX, , , VIH = MIN VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V 74ALS563A 74ALS564A VCC = MAX, VI = 0 4V MAX 0.4V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.4V VCC = MAX, VO = 2.25V ICCH 74ALS563A ICC Supply current (total) 74ALS564A ICCL ICCZ ICCH ICCL ICCZ VCC = MAX VCC = MAX -30 7 13 15 11 17 18 IOH = -0.4mA IOH = MAX IOL = 12mA IOL = 24mA VCC - 2 2.4 3.2 0.25 0.35 -0.73 0.40 0.50 -1.5 0.1 20 -0.1 -0.2 20 -20 -112 12 21 24 18 27 28 LIMITS TYP2 UNIT MAX V V V V V mA A mA mA A A mA mA mA mA mA mA mA
VO OL VIK II IIH IIL IOZH IOZL IO
Low level output voltage Low-level Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Output current3
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
1996 Jul 01
6
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to High or Low level Output disable time from High or Low level Maximum clock frequency Propagation delay CP to Qn Output enable time to High or Low level Output disable time from High or Low level 74ALS564A Waveform 3 Waveform 2 74ALS563A Waveform 6 Waveform 7 Waveform 6 Waveform 7 Waveform 1 Waveform 1 Waveform 6 Waveform 7 Waveform 6 Waveform 7 2.0 3.0 4.0 4.0 1.0 3.0 1.0 2.0 45 3.0 4.0 1.0 3.0 1.0 2.0 12.0 12.0 9.0 11.0 9.0 11.0 MAX 10.0 10.0 13.0 13.0 9.0 11.0 9.0 11.0 ns ns ns ns MHz ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tw(H) tsu(H) tsu(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low Dn to E Hold time, High or Low Dn to E E Pulse width, High Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP CP Pulse width, High or Low 74ALS564A 74ALS563A Waveform 4 Waveform 4 Waveform 1 Waveform 5 Waveform 5 Waveform 5 6.0 6.0 6.0 6.0 10.0 6.0 6.0 1.0 1.0 7.0 11.0 MAX ns ns ns ns ns ns UNIT
1996 Jul 01
7
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
AC WAVEFORMS
For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax CP V M tw(H) tPLH Qn VM tw(L) tPHL VM Qn VM VM E VM
tw(H) VM tPHL VM VM tPLH VM
SF00258
SF00259
Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Widths, and Maximum Clock Frequency
Waveform 2.
Propagation Delay for Enable to Output and Enable Pulse Width
Dn
VM tPLH
VM tPHL
Qn
VM
VM
SF00260
Waveform 3.
Propagation Delay for Data to Output
Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L) VM
E
VM
VM
CP
VM
SF00261
SF00262
Waveform 4.
Data Setup Time and Hold Times
Waveform 5.
Data Setup Time and Hold Times
OE
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OE
VM tPZL
VM tPLZ 3.5V VM VOL +0.3V
Qn, Qn
Qn, Qn
SC00114
SC00115
Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1996 Jul 01
8
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V NEGATIVE PULSE 90% VM 10% tTHL (tff) CL RL tw VM 10% tTLH (tr ) 0.3V 90% AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
RL
tTLH (tr ) 90%
tTHL (tf ) AMP (V) 90% VM tw 10% 0.3V
Test Circuit for 3-State Outputs SWITCH POSITION TEST SWITCH closed tPLZ, tPZL All other open
POSITIVE PULSE 10%
VM
Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate 1MHz tw 500ns tTLH 2.0ns tTHL 2.0ns
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
SC00072
1996 Jul 01
9
Philips Semiconductors
Product specification
Latch flip-flop
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1996 Jul 01
10
Philips Semiconductors
Product specification
Latch flip-flop
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1996 Jul 01
11
Philips Semiconductors
Product specification
Latch flip-flop
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1996 Jul 01 12

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